[PATCH] D97895: [RISCV] Starting fixing issues the prevent us from testing vXi64 intrinsics on RV32.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2454
+    // point.
+    //   vmv.v.x vX, hi
+    //   vsll.vx vX, vX, /*32*/
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I was thinking maybe we just need two slide1ups using SEW=32 with VL set to 2 so that we don't slide anything but the scalars we're inserting.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:102
+  // for the VL value to be used for the operation.
+  VMV_S_X_VL,
   // VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT sign
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I think @frasercrmck has a patch that adds VMV_S_XF_VL which I think I can migrate to once its committed.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D97895/new/

https://reviews.llvm.org/D97895