[PATCH] D97054: [MachineVerifier] Confirm that both ends of a tied def/use are live together
Philip Reames via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 3 14:42:28 PST 2021
reames updated this revision to Diff 327929.
reames added a comment.
Second attempt. Finally wrapped my head around the weird failures - they turned out to mostly be sub-register liveness cases. I'm definitely not clear on what the expected invariants are there, and intend to punt that part to someone who does in the future.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D97054/new/
https://reviews.llvm.org/D97054
Files:
llvm/lib/CodeGen/MachineVerifier.cpp
Index: llvm/lib/CodeGen/MachineVerifier.cpp
===================================================================
--- llvm/lib/CodeGen/MachineVerifier.cpp
+++ llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1728,6 +1728,11 @@
}
}
+static bool tiedOpsRewritten(const MachineFunction *MF) {
+ auto Prop = MachineFunctionProperties::Property::TiedOpsRewritten;
+ return MF->getProperties().hasProperty(Prop);
+}
+
void
MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
const MachineInstr *MI = MO->getParent();
@@ -1829,8 +1834,7 @@
// TiedOpsRewritten property to verify two-address constraints, this
// property will be set in twoaddressinstruction pass.
unsigned DefIdx;
- if (MF->getProperties().hasProperty(
- MachineFunctionProperties::Property::TiedOpsRewritten) &&
+ if (tiedOpsRewritten(MF) &&
MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
Reg != MI->getOperand(DefIdx).getReg())
report("Two-address instruction operands must be identical", MO, MONum);
@@ -2741,6 +2745,22 @@
hasDef = true;
if (MOI->isEarlyClobber())
isEarlyClobber = true;
+
+ if (tiedOpsRewritten(MF) && MOI->isTied() && Reg.isVirtual()) {
+ unsigned DefOpNum = std::distance(MI->operands_begin(), &*MOI);
+ unsigned UseOpNum = MI->findTiedOperandIdx(DefOpNum);
+ const MachineOperand &UseOp = MI->getOperand(UseOpNum);
+ // Both ends of a tied def must be the same interval. Exceptions:
+ // - use is undef, implicit or noreg (not a real read)
+ // - live interval has subranges (purely because this is complicated
+ // and we haven't implemented the precise check yet)
+ if (!UseOp.isUndef() && !UseOp.isImplicit() && UseOp.getReg() != 0 &&
+ LaneMask.none() && !LR.liveAt(VNI->def.getBaseIndex())) {
+ report("tied def w/o use in same live range", MI);
+ report_context(LR, Reg, LaneMask);
+ report_context(*VNI);
+ }
+ }
}
if (!hasDef) {
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