[PATCH] D97691: [SLP] Honor min/max regsize and min/max VF in vectorizeStores

[Anton Afanasyev via Phabricator via llvm-commits]

anton-afanasyev added inline comments.


================
Comment at: llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp:6076
     unsigned EltSize = R.getVectorElementSize(Operands[0]);
+    unsigned MaxElts = llvm::PowerOf2Floor(MaxVecRegSize / EltSize);
+
----------------
Good fix, how did we missed this? Looks like ceil and floor are equal in real life here.


================
Comment at: llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp:6081
+    // one element fits in a vector register, but that did not match the
+    // code. Maybe this check can be removed?
     if (MaxVecRegSize % EltSize != 0)
----------------
Since `llvm::PowerOf2Floor()` could return `0` for zero argument, I believe this check could be actually removed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97691/new/

https://reviews.llvm.org/D97691