[PATCH] D97485: PowerPC][AIX] Handle variadic vector formal arguments.

[Sean Fertile via Phabricator via llvm-commits]

sfertile updated this revision to Diff 327794.
sfertile marked an inline comment as not done.
sfertile added a comment.

- Add asserts that the ValNo of custom RegLocs match the ValNo of the custom MemLoc.
- Assert that we are targeting 32-bit codegen when we have 4 custom RegLocs.
- Add comments to the tests to make it easier to determine what is being tested.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97485/new/

https://reviews.llvm.org/D97485

Files:
  llvm/lib/Target/PowerPC/PPCCCState.h
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee-split.ll
  llvm/test/CodeGen/PowerPC/aix32-vector-vararg-callee.ll
  llvm/test/CodeGen/PowerPC/aix32-vector-vararg-caller-split.ll
  llvm/test/CodeGen/PowerPC/aix32-vector-vararg-fixed-callee.ll
  llvm/test/CodeGen/PowerPC/aix64-vector-vararg-callee.ll
  llvm/test/CodeGen/PowerPC/aix64-vector-vararg-fixed-callee.ll

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