[PATCH] D97858: [AArch64][SVE] Fold vector ZExt/SExt into gather loads where possible

[Joe Ellis via Phabricator via llvm-commits]

joechrisellis created this revision.
joechrisellis added reviewers: DavidTruby, bsmith, david-arm, peterwaller-arm.
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This commit folds sign- or zero-extended offsets into gather loads where
possible with a DAGCombine optimization.

As an example, the following code:

  1	#include <arm_sve.h>
  2
  3	svuint64_t func(svbool_t pred, const int32_t *base, svint64_t offsets) {
  4	  return svld1sw_gather_s64offset_u64(
  5	    pred, base, svextw_s64_x(pred, offsets)
  6	  );
  7	}

would previously lower to the following assembly:

  sxtw	z0.d, p0/m, z0.d
  ld1sw	{ z0.d }, p0/z, [x0, z0.d]
  ret

but now lowers to:

  ld1sw   { z0.d }, p0/z, [x0, z0.d, sxtw]
  ret


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97858

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-scaled-offset.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-unscaled-offset.ll

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