[llvm] 4f6d798 - [AVR] Add register aliases XL, YH, etc

Ayke van Laethem via llvm-commits llvm-commits at lists.llvm.org
Wed Mar 3 06:36:27 PST 2021


Author: Ayke van Laethem
Date: 2021-03-03T15:36:05+01:00
New Revision: 4f6d7985d47abd35b657dbc7195c93892726d5f4

URL: https://github.com/llvm/llvm-project/commit/4f6d7985d47abd35b657dbc7195c93892726d5f4
DIFF: https://github.com/llvm/llvm-project/commit/4f6d7985d47abd35b657dbc7195c93892726d5f4.diff

LOG: [AVR] Add register aliases XL, YH, etc

These aliases are sometimes used in assembly code and make the code more
readable. They are supported by avr-gcc too.

Differential Revision: https://reviews.llvm.org/D96492

Added: 
    llvm/test/MC/AVR/registers.s

Modified: 
    llvm/lib/Target/AVR/AVRRegisterInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AVR/AVRRegisterInfo.td b/llvm/lib/Target/AVR/AVRRegisterInfo.td
index ab5d02356c9d..6f3086d0b104 100644
--- a/llvm/lib/Target/AVR/AVRRegisterInfo.td
+++ b/llvm/lib/Target/AVR/AVRRegisterInfo.td
@@ -67,12 +67,12 @@ def R22 : AVRReg<22, "r22">, DwarfRegNum<[22]>;
 def R23 : AVRReg<23, "r23">, DwarfRegNum<[23]>;
 def R24 : AVRReg<24, "r24">, DwarfRegNum<[24]>;
 def R25 : AVRReg<25, "r25">, DwarfRegNum<[25]>;
-def R26 : AVRReg<26, "r26">, DwarfRegNum<[26]>;
-def R27 : AVRReg<27, "r27">, DwarfRegNum<[27]>;
-def R28 : AVRReg<28, "r28">, DwarfRegNum<[28]>;
-def R29 : AVRReg<29, "r29">, DwarfRegNum<[29]>;
-def R30 : AVRReg<30, "r30">, DwarfRegNum<[30]>;
-def R31 : AVRReg<31, "r31">, DwarfRegNum<[31]>;
+def R26 : AVRReg<26, "r26", [], ["xl"]>, DwarfRegNum<[26]>;
+def R27 : AVRReg<27, "r27", [], ["xh"]>, DwarfRegNum<[27]>;
+def R28 : AVRReg<28, "r28", [], ["yl"]>, DwarfRegNum<[28]>;
+def R29 : AVRReg<29, "r29", [], ["yh"]>, DwarfRegNum<[29]>;
+def R30 : AVRReg<30, "r30", [], ["zl"]>, DwarfRegNum<[30]>;
+def R31 : AVRReg<31, "r31", [], ["zh"]>, DwarfRegNum<[31]>;
 def SPL : AVRReg<32, "SPL">, DwarfRegNum<[32]>;
 def SPH : AVRReg<33, "SPH">, DwarfRegNum<[33]>;
 

diff  --git a/llvm/test/MC/AVR/registers.s b/llvm/test/MC/AVR/registers.s
new file mode 100644
index 000000000000..62872a83a87c
--- /dev/null
+++ b/llvm/test/MC/AVR/registers.s
@@ -0,0 +1,33 @@
+; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
+; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s
+
+; Test register aliases: the upper 6 registers have aliases that can be used in
+; assembly.
+
+foo:
+  inc xl
+  inc xh
+  inc yl
+  inc yh
+  inc zl
+  inc zh
+
+  inc XL ; test uppercase
+
+; CHECK: inc r26                    ; encoding: [0xa3,0x95]
+; CHECK: inc r27                    ; encoding: [0xb3,0x95]
+; CHECK: inc r28                    ; encoding: [0xc3,0x95]
+; CHECK: inc r29                    ; encoding: [0xd3,0x95]
+; CHECK: inc r30                    ; encoding: [0xe3,0x95]
+; CHECK: inc r31                    ; encoding: [0xf3,0x95]
+
+; CHECK: inc r26                    ; encoding: [0xa3,0x95]
+
+; CHECK-INST: inc r26
+; CHECK-INST: inc r27
+; CHECK-INST: inc r28
+; CHECK-INST: inc r29
+; CHECK-INST: inc r30
+; CHECK-INST: inc r31
+
+; CHECK-INST: inc r26


        


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