[PATCH] D97840: [AArch64] Legalize horizontal fmax/fmin reductions on f16 vectors

[LemonBoy via Phabricator via llvm-commits]

LemonBoy marked 4 inline comments as done.
LemonBoy added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10488
+    if (SrcVT.getVectorElementType() == MVT::f16 && !Subtarget->hasFullFP16())
+      return SDValue();
+
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nikic wrote:
> Might be better to not mark them Custom in the first place? https://github.com/llvm/llvm-project/blob/3b47bd32f9df4a57db98db5f35e680c7bd9fde3e/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L1019-L1023
Indeed, fixed.
Thanks for the suggestion!


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Comment at: llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll:67
 
+define half @test_v4f16(<4 x half> %a) nounwind {
+; CHECK-LABEL: test_v4f16:
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fhahn wrote:
> can you also throw in a test with vectors that are not directly legal, regardless of `fullfp16`?
That's hitting a different problem in the legalization step, I'll try to address that in a separate patch.


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  https://reviews.llvm.org/D97840/new/

https://reviews.llvm.org/D97840