[PATCH] D97840: [AArch64] Legalize horizontal fmax/fmin reductions on f16 vectors

[Nikita Popov via Phabricator via llvm-commits]

nikic added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10488
+    if (SrcVT.getVectorElementType() == MVT::f16 && !Subtarget->hasFullFP16())
+      return SDValue();
+
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Might be better to not mark them Custom in the first place? https://github.com/llvm/llvm-project/blob/3b47bd32f9df4a57db98db5f35e680c7bd9fde3e/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L1019-L1023


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D97840/new/

https://reviews.llvm.org/D97840