[PATCH] D97840: [AArch64] Legalize horizontal fmax/fmin reductions on f16 vectors

[Florian Hahn via Phabricator via llvm-commits]

fhahn added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll:3
 ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
+; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon,+fullfp16 | FileCheck %s --check-prefix=FP16
 
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david-arm wrote:
> Hi, instead of having two RUN lines here would it be better to just use function attributes, i.e. for test_v4f16 have a function attribute that adds "fullfp16" support? That way you only need one RUN line and can avoid all the additional FP16 check lines too, since most of them seem to be the same as the first RUN line.
You could also use multiple check prefixes to avoid having repeated check for both RUN lines, if they are equal, e.g. `FileCheck %s --check-prefix=CHECK --check-prefix=NOFP16 ...`,  `FileCheck %s --check-prefix=CHECK --check-prefix=FP16 ...`

With that, we should only need separate `FP16`/`NOFP16` check lines for functions where there is a difference.


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  https://reviews.llvm.org/D97840/new/

https://reviews.llvm.org/D97840