[PATCH] D97840: [AArch64] Legalize horizontal fmax/fmin reductions on f16 vectors

[LemonBoy via Phabricator via llvm-commits]

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Expand the horizontal reduction during the instruction selection phase, but only if the target doesn't support the full fp16 instruction set.

Fixes https://bugs.llvm.org/show_bug.cgi?id=49401


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97840

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
  llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll

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