[PATCH] D94928: [llvm-mca] Add support for in-order CPUs

[Andrew Savonichev via Phabricator via llvm-commits]

asavonic added inline comments.


================
Comment at: llvm/lib/MCA/Stages/InOrderIssueStage.cpp:83
+        // Try again in the next cycle
+        return 1;
+      }
----------------
andreadb wrote:
> As I wrote before, you should simply ignore the case where the number of cycles left is equal to UNKNOWN_CYCLES.
> You shouldn't early exit with an arbitrary number of cycles.
> 
> Basically what I am saying is that you should replace this return statement with a `continue;`
> As I wrote before, you should simply ignore the case where the number of cycles left is equal to UNKNOWN_CYCLES.
> You shouldn't early exit with an arbitrary number of cycles.
> 
> Basically what I am saying is that you should replace this return statement with a `continue;`

I mentioned this above, but I might be missing something.

What exactly UNKNOWN_CYCLES means in this case? I assume that for in-order
pipeline it means that an instruction is issued (since we issue in-order), but
we don't know when its write is going to be completed. If this is correct, then
we should not issue any instructions that depend on this write until we know that the write
is completed (and has CyclesLeft == 0).

`return 1` here stalls the instruction for 1 cycle, and it will be checked again
in the next cycle. If we `continue` here instead, then the write is ignored.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94928/new/

https://reviews.llvm.org/D94928