[PATCH] D94928: [llvm-mca] Add support for in-order CPUs

[Andrew Savonichev via Phabricator via llvm-commits]

asavonic updated this revision to Diff 327409.
asavonic added a comment.

Supported UNKNOWN_CYCLES left and negative ReadAdvance.
Disabled bottleneck analysis for in-order CPUs.
Updated documentation.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94928/new/

https://reviews.llvm.org/D94928

Files:
  llvm/docs/CommandGuide/llvm-mca.rst
  llvm/docs/ReleaseNotes.rst
  llvm/include/llvm/MC/MCSchedule.h
  llvm/include/llvm/MCA/Context.h
  llvm/include/llvm/MCA/HardwareUnits/RegisterFile.h
  llvm/include/llvm/MCA/HardwareUnits/RetireControlUnit.h
  llvm/include/llvm/MCA/Instruction.h
  llvm/include/llvm/MCA/Stages/InOrderIssueStage.h
  llvm/include/llvm/MCA/Stages/RetireStage.h
  llvm/include/llvm/Target/TargetSchedule.td
  llvm/lib/MCA/CMakeLists.txt
  llvm/lib/MCA/Context.cpp
  llvm/lib/MCA/HardwareUnits/RetireControlUnit.cpp
  llvm/lib/MCA/InstrBuilder.cpp
  llvm/lib/MCA/Stages/InOrderIssueStage.cpp
  llvm/lib/MCA/Stages/RetireStage.cpp
  llvm/lib/Target/AArch64/AArch64SchedA55.td
  llvm/test/TableGen/InvalidMCSchedClassDesc.td
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-add-sequence.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-in-order-retire.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-out-of-order-retire.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/in-order-bottleneck-analysis.s
  llvm/test/tools/llvm-mca/ARM/m7-negative-readadvance.s
  llvm/test/tools/llvm-mca/X86/in-order-cpu.s
  llvm/tools/llvm-mca/llvm-mca.cpp
  llvm/utils/TableGen/SubtargetEmitter.cpp

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