[PATCH] D97582: [LegalizeVectorTypes] Improve SplitVecRes_INSERT_SUBVECTOR to handle subvector being in the high half of the split or not at element 0 of the low half.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

LGTM other than my final nit.



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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:1271
   unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
-  if ((IdxVal == 0) && (IdxVal + SubElems <= VecElems / 2)) {
-    EVT LoVT, HiVT;
-    std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
+  if (IdxVal >= 0 && (IdxVal + SubElems <= LoElems)) {
     Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
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While we're changing these lines, I'm not sure this style of parentheses around subexpressions is common?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D97582/new/

https://reviews.llvm.org/D97582