[llvm] d6ba8ec - [ARM] Add handling of t2LDRSB/t2LDRSH in Constant Island Pass
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 2 00:46:22 PST 2021
Author: David Green
Date: 2021-03-02T08:46:07Z
New Revision: d6ba8ecb60f2a2365b5fc79f5a1557a2490f7b68
URL: https://github.com/llvm/llvm-project/commit/d6ba8ecb60f2a2365b5fc79f5a1557a2490f7b68
DIFF: https://github.com/llvm/llvm-project/commit/d6ba8ecb60f2a2365b5fc79f5a1557a2490f7b68.diff
LOG: [ARM] Add handling of t2LDRSB/t2LDRSH in Constant Island Pass
These constant pool loads should be treated similarly to t2LDRB/t2LDRH,
acting on the same offset ranges. Add handling and a simple test.
Added:
llvm/test/CodeGen/Thumb2/constant-islands-ldrsb.mir
Modified:
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
index 0bb595b21107..a23e65aa9659 100644
--- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -850,7 +850,9 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
case ARM::LDRcp:
case ARM::t2LDRpci:
case ARM::t2LDRHpci:
+ case ARM::t2LDRSHpci:
case ARM::t2LDRBpci:
+ case ARM::t2LDRSBpci:
Bits = 12; // +-offset_12
NegOk = true;
break;
diff --git a/llvm/test/CodeGen/Thumb2/constant-islands-ldrsb.mir b/llvm/test/CodeGen/Thumb2/constant-islands-ldrsb.mir
new file mode 100644
index 000000000000..776f0f705dd2
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/constant-islands-ldrsb.mir
@@ -0,0 +1,59 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -run-pass=arm-cp-islands -o - %s | FileCheck %s
+
+# CHECK-NOT: Unknown addressing mode for CP reference
+
+--- |
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+ target triple = "thumbv8.1m.main-arm-none-eabi"
+
+ define void @t2LDRSBpci() { ret void }
+ define void @t2LDRSHpci() { ret void }
+
+...
+---
+name: t2LDRSBpci
+alignment: 4
+tracksRegLiveness: true
+constants:
+ - id: 0
+ value: 'i32 0'
+ alignment: 4
+body: |
+ bb.0:
+ $sp = frame-setup tSUBspi $sp, 3, 14 /* CC::al */, $noreg
+ frame-setup CFI_INSTRUCTION def_cfa_offset 12
+ renamable $r0 = t2LDRSBpci %const.0, 14 /* CC::al */, $noreg :: (dereferenceable load 1, align 4)
+ renamable $r1 = tMOVr $sp, 14 /* CC::al */, $noreg
+ tCMPr killed renamable $r1, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ $r1 = t2MOVi16 target-flags(arm-lo16) @t2LDRSBpci, 14 /* CC::al */, $noreg
+ renamable $r0 = t2CSINC $zr, $zr, 3, implicit killed $cpsr
+ $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @t2LDRSBpci, 14 /* CC::al */, $noreg
+ tSTRi killed renamable $r0, killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (store 4)
+ $sp = frame-destroy tADDspi $sp, 3, 14 /* CC::al */, $noreg
+ tBX_RET 14 /* CC::al */, $noreg
+
+...
+---
+name: t2LDRSHpci
+alignment: 4
+tracksRegLiveness: true
+constants:
+ - id: 0
+ value: 'i32 0'
+ alignment: 4
+body: |
+ bb.0:
+ $sp = frame-setup tSUBspi $sp, 3, 14 /* CC::al */, $noreg
+ frame-setup CFI_INSTRUCTION def_cfa_offset 12
+ renamable $r0 = t2LDRSHpci %const.0, 14 /* CC::al */, $noreg :: (dereferenceable load 1, align 4)
+ renamable $r1 = tMOVr $sp, 14 /* CC::al */, $noreg
+ tCMPr killed renamable $r1, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
+ $r1 = t2MOVi16 target-flags(arm-lo16) @t2LDRSHpci, 14 /* CC::al */, $noreg
+ renamable $r0 = t2CSINC $zr, $zr, 3, implicit killed $cpsr
+ $r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @t2LDRSHpci, 14 /* CC::al */, $noreg
+ tSTRi killed renamable $r0, killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (store 4)
+ $sp = frame-destroy tADDspi $sp, 3, 14 /* CC::al */, $noreg
+ tBX_RET 14 /* CC::al */, $noreg
+
+...
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