[PATCH] D97570: [dfsan] Propagate origin tracking at load

Matt Morehouse via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Mar 1 15:32:37 PST 2021


morehouse added inline comments.


================
Comment at: llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp:579
   Value *combineOperandShadows(Instruction *Inst);
-  Value *loadShadow(Value *ShadowAddr, uint64_t Size, uint64_t Align,
-                    Instruction *Pos);
+  std::pair<Value *, Value *> loadShadowOrigin(Value *ShadowAddr, uint64_t Size,
+                                               Align InstAlignment,
----------------
gbalats wrote:
> I think it would be cleaner if we retained the older function (with its older return value) and introduced a new one:
> loadShadowAndOrigin
+1


================
Comment at: llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp:1892
+  // * if Size == 2, we assume most cases Addr % 2 == 0, so it is sufficient to
+  //   load its origin aligned at 4. If not, althought origins may be lost, it
+  //   should not happen very often.
----------------



================
Comment at: llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp:2027
+
+  // Non-scaped load.
   if (AllocaInst *AI = dyn_cast<AllocaInst>(Addr)) {
----------------
What does "non-scaped" mean?


================
Comment at: llvm/test/Instrumentation/DataFlowSanitizer/origin_ldst.ll:243
+  ; NO_COMBINE_LOAD_PTR-NEXT: %a = load i17, i17* %p, align 4
+  ; NO_COMBINE_LOAD_PTR-NEXT: store i16 [[LABLE]], i16* bitcast ([100 x i64]* @__dfsan_retval_tls to i16*), align 2
+  ; NO_COMBINE_LOAD_PTR-NEXT: store i32 [[ORIGIN]], i32* @__dfsan_retval_origin_tls, align 4
----------------
Nit:  s/LABLE/LABEL


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97570/new/

https://reviews.llvm.org/D97570



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