[PATCH] D89693: [AArch64] Favor pre-increments and implement TTI::getPreferredAddressingMode

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer updated this revision to Diff 327124.
SjoerdMeijer retitled this revision from "[AArch64] Favor post-increments and implement TTI::getPreferredAddressingMode" to "[AArch64] Favor pre-increments and implement TTI::getPreferredAddressingMode".
SjoerdMeijer edited the summary of this revision.
SjoerdMeijer added reviewers: stelios-arm, NickGuy.
SjoerdMeijer added a comment.

This is changing our approach to preferring pre-indexed addressing modes, because:

- this what we want for runtime unrolled loops, which is what we want to address next,
- post indexed is currently better for some cases, but that's mainly cause because we miss an opportunity in the load/store optimiser. With that fixed, expectation is that pre-indexed gives the same or better perf than post-indexed.
- for what it is worth, pre-indexed is also the default for ARM,

And as a consequence of the above, this implementation becomes really straightforward, which is another benefit. 
But again, we can't commit this yet, because it depends on changes in the load/store optimiser which we will address first.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89693/new/

https://reviews.llvm.org/D89693

Files:
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h
  llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
  llvm/test/CodeGen/AArch64/arm64-scaled_iv.ll
  llvm/test/CodeGen/AArch64/falkor-hwpf-fix.ll
  llvm/test/CodeGen/AArch64/pr27816.ll
  llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
  llvm/test/CodeGen/AArch64/vldn_shuffle.ll
  llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-memcpy.ll
  llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-memset.ll

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