[llvm] 361cfdf - GlobalISel: Verify G_CONCAT_VECTORS has at least 2 sources

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2021-03-01T09:10:36-05:00
New Revision: 361cfdf2284193365f2830008625975f55112428

URL: https://github.com/llvm/llvm-project/commit/361cfdf2284193365f2830008625975f55112428
DIFF: https://github.com/llvm/llvm-project/commit/361cfdf2284193365f2830008625975f55112428.diff

LOG: GlobalISel: Verify G_CONCAT_VECTORS has at least 2 sources

Added: 
    

Modified: 
    llvm/lib/CodeGen/MachineVerifier.cpp
    llvm/test/MachineVerifier/test_g_concat_vectors.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index a248e54217ff..8bae5ab0bde3 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1285,6 +1285,10 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
     if (!DstTy.isVector() || !SrcTy.isVector())
       report("G_CONCAT_VECTOR requires vector source and destination operands",
              MI);
+
+    if (MI->getNumOperands() < 3)
+      report("G_CONCAT_VECTOR requires at least 2 source operands", MI);
+
     for (unsigned i = 2; i < MI->getNumOperands(); ++i) {
       if (MRI->getType(MI->getOperand(1).getReg()) !=
           MRI->getType(MI->getOperand(i).getReg()))

diff  --git a/llvm/test/MachineVerifier/test_g_concat_vectors.mir b/llvm/test/MachineVerifier/test_g_concat_vectors.mir
index 6f1f51e3168f..b24401db1399 100644
--- a/llvm/test/MachineVerifier/test_g_concat_vectors.mir
+++ b/llvm/test/MachineVerifier/test_g_concat_vectors.mir
@@ -1,29 +1,25 @@
 #RUN: not --crash llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
 # REQUIRES: aarch64-registered-target
---- |
-  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
-  target triple = "aarch64-unknown-unknown"
-  
-  define i32 @g_concat_vectors() {
-    ret i32 0
-  }
-
-...
 ---
 name:            g_concat_vectors
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
-registers:       
-  - { id: 0, class: _, preferred-register: '' }
-  - { id: 1, class: _, preferred-register: '' }
-liveins:         
+liveins:
 body:             |
   bb.0:
-    ; CHECK: Bad machine code: G_CONCAT_VECTOR num dest and source elements should match
 
-    %0(<2 x s32>) = IMPLICIT_DEF
-    %1(<2 x s32>) = IMPLICIT_DEF
+    %0:_(<2 x s32>) = IMPLICIT_DEF
+    %1:_(<2 x s32>) = IMPLICIT_DEF
+
+    ; CHECK: Bad machine code: G_CONCAT_VECTOR num dest and source elements should match
     %2:_(<2 x s32>) = G_CONCAT_VECTORS %0, %1
+
+    ; CHECK: Bad machine code: G_CONCAT_VECTOR requires at least 2 source operands
+    %3:_(<2 x s32>) = G_CONCAT_VECTORS %1
+
+    ; CHECK: *** Bad machine code: Explicit definition marked as use ***
+    G_CONCAT_VECTORS %1, %1
+
 ...