[PATCH] D97624: [X86] Improve SMULO/UMULO codegen for vXi8 vectors.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:27396
+                                     SelectionDAG &DAG,
+                                     SDValue *Low = nullptr) {
+  unsigned NumElts = VT.getVectorNumElements();
----------------
RKSimon wrote:
> Isn't this really ISD::SMUL_LOHI/UMUL_LOHI ? Could the legalizer be taught to try and use as well?
The legalizer will try to use SMUL_LOHI/UMUL_LOHI, but I think it tries MULHS/MULHU+MUL first. I suppose scalar was the main consideration there where targets don't usually have both so the order of checking them doesn't matter.

Maybe we could implement SMUL_LOHI/UMUL_LOHI for v16i8 and not MULHS/MULHU. Then fix LegalizeVectorOps to expand MULHS/MULHU to SMUL_LOHI/UMUL_LOHI? It doesn't now and would end up scalarizing if it sees a MULHS/MULHU.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97624/new/

https://reviews.llvm.org/D97624