[PATCH] D97582: [LegalizeVectorTypes] Improve SplitVecRes_INSERT_SUBVECTOR to handle subvector being in the high half of the split or not at element 0 of the low half.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Feb 26 14:46:49 PST 2021


craig.topper created this revision.
craig.topper added reviewers: frasercrmck, RKSimon, spatel.
Herald added a subscriber: hiraditya.
craig.topper requested review of this revision.
Herald added a project: LLVM.

This function isn't exercised in lit tests today today according to
the code coverage report. But will be after the tests in D97543 <https://reviews.llvm.org/D97543> and
D97559 <https://reviews.llvm.org/D97559>.

Posting this patch to help a crash that Fraser hit.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97582

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -1261,19 +1261,24 @@
   unsigned VecElems = VecVT.getVectorNumElements();
   unsigned SubElems = SubVec.getValueType().getVectorNumElements();
 
-  // If we know the index is 0, and we know the subvector doesn't cross the
-  // boundary between the halves, we can avoid spilling the vector, and insert
-  // into the lower half of the split vector directly.
-  // TODO: The IdxVal == 0 constraint is artificial, we could do this whenever
-  // there is no boundary crossing. But those cases don't seem to get hit in
-  // practice.
+  // If we know the index is in the first half, and we know the subvector
+  // doesn't cross the/ boundary between the halves, we can avoid spilling the
+  // vector, and insert into the lower half of the split vector directly.
+  // Similarly if the subvector is fully in the high half.
   unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
-  if ((IdxVal == 0) && (IdxVal + SubElems <= VecElems / 2)) {
+  if (IdxVal >= 0 && (IdxVal + SubElems <= VecElems / 2)) {
     EVT LoVT, HiVT;
     std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
     Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
     return;
   }
+  if ((IdxVal >= VecElems / 2) && (IdxVal + SubElems <= VecElems)) {
+    EVT LoVT, HiVT;
+    std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
+    Hi = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, HiVT, Hi, SubVec,
+                     DAG.getVectorIdxConstant(IdxVal - (VecElems / 2), dl));
+    return;
+  }
 
   // Spill the vector to the stack.
   // In cases where the vector is illegal it will be broken down into parts


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D97582.326807.patch
Type: text/x-patch
Size: 1878 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210226/40a4dfbd/attachment.bin>


More information about the llvm-commits mailing list