[PATCH] D97571: [AArch64] Fix emitting an AdrpAddLdr LOH when there's a potential clobber of the def of the adrp before the ldr.

[Quentin Colombet via Phabricator via llvm-commits]

qcolombet accepted this revision.
qcolombet added inline comments.
This revision is now accepted and ready to land.


================
Comment at: llvm/lib/Target/AArch64/AArch64CollectLOH.cpp:444
+      if (AddMI->getIterator() == EndIt || LdrMI != &*next_nodbg(AddIt, EndIt))
+        break;
+
----------------
I think `AddMI->getIterator() == EndIt` shouldn't be possible, otherwise we won't have a load in MI2.

I haven't looked at that code for a long time but I think that when you'll look for a proper fix, you should be able to use `handleClobber` to accumulate the registers that are clobbered between two instructions.

You may actually use that right now to still only issue this LOH when all the possible optimizations are safe.


Repository:
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  https://reviews.llvm.org/D97571/new/

https://reviews.llvm.org/D97571