[PATCH] D97406: [Vectorizers]Improve emission of logical or/and reductions.
Alexey Bataev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 26 07:59:45 PST 2021
ABataev added a comment.
Yeah, I also thought about moving this to instcombiner. This patch originally is more a question where it is better to implement it. I'll move the transformation to the instcombiner.
================
Comment at: llvm/lib/Transforms/Utils/LoopUtils.cpp:1031
auto *SrcVecEltTy = cast<VectorType>(Src->getType())->getElementType();
+ if ((RdxKind == RecurKind::And || RdxKind == RecurKind::Or) &&
+ SrcVecEltTy == Builder.getInt1Ty()) {
----------------
sdesmalen wrote:
> Can you add the condition that `&& isa<FixedVectorType>(Src)`? (same request for LoopVectorize.cpp and SLPVectorize.cpp)
>
> We're starting to make the LoopVectorizer vectorize for scalable VFs. This means we're currently fixing up cases like this where assumptions are made that are only valid for fixed-width vectors. For scalable vectors it might be possible to do the `<vscale x N x i1>` reduction as a compare on `<vscale x 1 x iN>`, but at least for SVE I know that we never want that.
Sure, will do.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D97406/new/
https://reviews.llvm.org/D97406
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