[PATCH] D97480: [RISCV] Support inline asm for vector instructions.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6218
+      // PartVT first.
+      if (ValueEltVT != PartEltVT) {
+        unsigned Count = ValueVTBitSize / PartEltVT.getSizeInBits();
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HsiangKai wrote:
> frasercrmck wrote:
> > In what situations are the element types not equal? Does the PartVT come from the first type in the RC?
> Yes, the PartVT comes from the first type in the RC. Another way to handle it is to search the corresponding type in the RC in GetRegistersForValue(). The problem comes from we reuse VR register class for fractional LMUL types.
Thanks! (Un)Luckily I've seen the "first type" issue before: I wish there was a better way.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6219
+      if (ValueEltVT != PartEltVT) {
+        unsigned Count = ValueVTBitSize / PartEltVT.getSizeInBits();
+        EVT SameEltTypeVT = EVT::getVectorVT(Context, PartEltVT, Count, true);
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HsiangKai wrote:
> frasercrmck wrote:
> > Is this guaranteed not to become 0?
> Yes, I reordered the supported types in VR. The first type has the element type i8. In addition, I created VM register class for mask register types.
Cool. Then perhaps we can check/assert on this, just so the types aren't accidentally reordered in the future? This seems to me like quite a few implicit dependencies being used and handed to us via this method.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D97480/new/

https://reviews.llvm.org/D97480