[PATCH] D97549: [RISCV] Improve support of LoopVectorizer for RISC-V Vector

[Luke via Phabricator via llvm-commits]

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Improve support of LoopVectorizer for RISC-V Vector by implementing unsigned RISCVTTIImpl::getRegisterBitWidth(bool Vector).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97549

Files:
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h


Index: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -51,6 +51,16 @@
   bool shouldExpandReduction(const IntrinsicInst *II) const;
   bool supportsScalableVectors() const { return ST->hasStdExtV(); }
   Optional<unsigned> getMaxVScale() const;
+
+  unsigned getRegisterBitWidth(bool Vector) const {
+    if (Vector) {
+      if (ST->hasStdExtV())
+        return std::max(ST->getMinRVVVectorSizeInBits(), 128u);
+      return 0;
+    }
+    return ST->getXLen();
+  }
+
 };

 } // end namespace llvm


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