[PATCH] D97480: [RISCV] Support inline asm for vector instructions.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:6214
+    unsigned ValueVTBitSize =
+        ValueVT.getVectorElementCount().getKnownMinValue() *
+        ValueEltVT.getSizeInBits();
----------------
ValueVT.getVectorElementCount().getKnownMinValue() is equivalents to ValueVT.getVectorMinNumElements() I think.

Or would ValueVT.getSizeInBits().getKnownMinValue() replace the whole thing?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97480/new/

https://reviews.llvm.org/D97480