[PATCH] D97274: [RISCV] replace unuseful emergency spill slot test with a mir test
Luís Marques via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 25 09:12:47 PST 2021
luismarques added a comment.
>From some quick testing, it seemed that you could trim this test down a bit.
You're also adding `# REQUIRES: asserts` but not actually checking for any debug output.
Also, it would be nice to add a comment documenting the logic of this test, unless new `CHECK`s of the debug output make it more obvious.
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D97274/new/
https://reviews.llvm.org/D97274
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