[PATCH] D97274: [RISCV] replace unuseful emergency spill slot test with a mir test

[Luís Marques via Phabricator via llvm-commits]

luismarques added a comment.

>From some quick testing, it seemed that you could trim this test down a bit.
You're also adding `# REQUIRES: asserts` but not actually checking for any debug output.
Also, it would be nice to add a comment documenting the logic of this test, unless new `CHECK`s of the debug output make it more obvious.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97274/new/

https://reviews.llvm.org/D97274