[llvm] 25c6b7d - [RISCV] Add isel pattern to match X > -1 to bgez.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-02-25T07:42:22-08:00
New Revision: 25c6b7ddd2b4d9631d0aff312b076843c16239d7

URL: https://github.com/llvm/llvm-project/commit/25c6b7ddd2b4d9631d0aff312b076843c16239d7
DIFF: https://github.com/llvm/llvm-project/commit/25c6b7ddd2b4d9631d0aff312b076843c16239d7.diff

LOG: [RISCV] Add isel pattern to match X > -1 to bgez.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D97262

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td
    llvm/test/CodeGen/RISCV/branch.ll
    llvm/test/CodeGen/RISCV/xaluo.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index b7deb3a766af..b2f5fb3a773c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -990,6 +990,10 @@ def : Pat<(brcond GPR:$cond, bb:$imm12), (BNE GPR:$cond, X0, bb:$imm12)>;
 def : Pat<(brcond (XLenVT (xor GPR:$cond, 1)), bb:$imm12),
           (BEQ GPR:$cond, X0, bb:$imm12)>;
 
+// Match X > -1, the canonical form of X >= 0, to the bgez pattern.
+def : Pat<(brcond (XLenVT (setgt GPR:$rs1, -1)), bb:$imm12),
+          (BGE GPR:$rs1, X0, bb:$imm12)>;
+
 let isBarrier = 1, isBranch = 1, isTerminator = 1 in
 def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>,
                PseudoInstExpansion<(JAL X0, simm21_lsb0_jal:$imm20)>;

diff  --git a/llvm/test/CodeGen/RISCV/branch.ll b/llvm/test/CodeGen/RISCV/branch.ll
index b118dfb4bfde..065c00bbb279 100644
--- a/llvm/test/CodeGen/RISCV/branch.ll
+++ b/llvm/test/CodeGen/RISCV/branch.ll
@@ -40,8 +40,7 @@ define void @foo(i32 %a, i32 *%b, i1 %c) nounwind {
 ; RV32I-NEXT:    bnez a0, .LBB0_13
 ; RV32I-NEXT:  # %bb.11: # %test12
 ; RV32I-NEXT:    lw a0, 0(a1)
-; RV32I-NEXT:    addi a2, zero, -1
-; RV32I-NEXT:    blt a2, a0, .LBB0_13
+; RV32I-NEXT:    bgez a0, .LBB0_13
 ; RV32I-NEXT:  # %bb.12: # %test13
 ; RV32I-NEXT:    lw a0, 0(a1)
 ; RV32I-NEXT:  .LBB0_13: # %end

diff  --git a/llvm/test/CodeGen/RISCV/xaluo.ll b/llvm/test/CodeGen/RISCV/xaluo.ll
index 6d0652840322..e7772026fce1 100644
--- a/llvm/test/CodeGen/RISCV/xaluo.ll
+++ b/llvm/test/CodeGen/RISCV/xaluo.ll
@@ -1538,8 +1538,7 @@ define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    not a1, a1
 ; RV32-NEXT:    and a0, a1, a0
-; RV32-NEXT:    addi a1, zero, -1
-; RV32-NEXT:    blt a1, a0, .LBB47_2
+; RV32-NEXT:    bgez a0, .LBB47_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    mv a0, zero
 ; RV32-NEXT:    ret
@@ -1706,8 +1705,7 @@ define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
 ; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    xor a1, a1, a3
 ; RV32-NEXT:    and a0, a1, a0
-; RV32-NEXT:    addi a1, zero, -1
-; RV32-NEXT:    blt a1, a0, .LBB51_2
+; RV32-NEXT:    bgez a0, .LBB51_2
 ; RV32-NEXT:  # %bb.1: # %overflow
 ; RV32-NEXT:    mv a0, zero
 ; RV32-NEXT:    ret