[PATCH] D42981: [COST] Fix cost model of load instructions on X86

Thu Feb 25 07:22:33 PST 2021

RKSimon added a comment.

I have a few concerns

- we're increasing register pressure (x86 fp scalars share regs with the vector types)
- I'm not certain we are accounting for the impact of increased AGU usage - even though the load has been folded "for free", are we correctly handling the gep costs?

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Comment at: llvm/test/Transforms/LoopVectorize/X86/pr34438.ll:35
+; CHECK-NEXT:    store <4 x float> [[TMP7]], <4 x float>* [[TMP8]], align 4, !llvm.access.group !0
+; CHECK-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 4
 ; CHECK-NEXT:    [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], 8
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This looks like a VECTOR regression on AVX targets?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D42981/new/

https://reviews.llvm.org/D42981