[PATCH] D97467: [RISCV] Use existing method for the LMUL1 type. NFCI.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck created this revision.
frasercrmck added reviewers: craig.topper, rogfer01, HsiangKai, arcbbb, khchen, evandro.
Herald added subscribers: vkmr, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
frasercrmck requested review of this revision.
Herald added subscribers: llvm-commits, MaskRay.
Herald added a project: LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97467

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp


Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2326,6 +2326,14 @@
   return SDValue(); // Don't custom lower most intrinsics.
 }
 
+static MVT getLMUL1VT(MVT VT) {
+  assert(VT.getVectorElementType().getSizeInBits() <= 64 &&
+         "Unexpected vector MVT");
+  return MVT::getScalableVectorVT(
+      VT.getVectorElementType(),
+      RISCV::RVVBitsPerBlock / VT.getVectorElementType().getSizeInBits());
+}
+
 static std::pair<unsigned, uint64_t>
 getRVVReductionOpAndIdentityVal(unsigned ISDOpcode, unsigned EltSizeBits) {
   switch (ISDOpcode) {
@@ -2359,18 +2367,13 @@
   assert(Op.getValueType().isSimple() &&
          Op.getOperand(0).getValueType().isSimple() &&
          "Unexpected vector-reduce lowering");
-  MVT VecEltVT = Op.getOperand(0).getSimpleValueType().getVectorElementType();
+  MVT VecVT = Op.getOperand(0).getSimpleValueType();
+  MVT VecEltVT = VecVT.getVectorElementType();
   unsigned RVVOpcode;
   uint64_t IdentityVal;
   std::tie(RVVOpcode, IdentityVal) =
       getRVVReductionOpAndIdentityVal(Op.getOpcode(), VecEltVT.getSizeInBits());
-  // We have to perform a bit of a dance to get from our vector type to the
-  // correct LMUL=1 vector type. We divide our minimum VLEN (64) by the vector
-  // element type to find the type which fills a single register. Be careful to
-  // use the operand's vector element type rather than the reduction's value
-  // type, as that has likely been extended to XLEN.
-  unsigned NumElts = 64 / VecEltVT.getSizeInBits();
-  MVT M1VT = MVT::getScalableVectorVT(VecEltVT, NumElts);
+  MVT M1VT = getLMUL1VT(VecVT);
   SDValue IdentitySplat =
       DAG.getSplatVector(M1VT, DL, DAG.getConstant(IdentityVal, DL, VecEltVT));
   SDValue Reduction =
@@ -2402,30 +2405,19 @@
                                               SelectionDAG &DAG) const {
   SDLoc DL(Op);
   MVT VecEltVT = Op.getSimpleValueType();
-  // We have to perform a bit of a dance to get from our vector type to the
-  // correct LMUL=1 vector type. See above for an explanation.
-  unsigned NumElts = 64 / VecEltVT.getSizeInBits();
-  MVT M1VT = MVT::getScalableVectorVT(VecEltVT, NumElts);
 
   unsigned RVVOpcode;
   SDValue VectorVal, ScalarVal;
   std::tie(RVVOpcode, VectorVal, ScalarVal) =
       getRVVFPReductionOpAndOperands(Op, DAG, VecEltVT);
 
+  MVT M1VT = getLMUL1VT(VectorVal.getSimpleValueType());
   SDValue ScalarSplat = DAG.getSplatVector(M1VT, DL, ScalarVal);
   SDValue Reduction = DAG.getNode(RVVOpcode, DL, M1VT, VectorVal, ScalarSplat);
   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VecEltVT, Reduction,
                      DAG.getConstant(0, DL, Subtarget.getXLenVT()));
 }
 
-static MVT getLMUL1VT(MVT VT) {
-  assert(VT.getVectorElementType().getSizeInBits() <= 64 &&
-         "Unexpected vector MVT");
-  return MVT::getScalableVectorVT(
-      VT.getVectorElementType(),
-      RISCV::RVVBitsPerBlock / VT.getVectorElementType().getSizeInBits());
-}
-
 SDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
                                                    SelectionDAG &DAG) const {
   SDValue Vec = Op.getOperand(0);


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