[PATCH] D96336: [AMDGPU] Save VGPR of whole wave when spilling

[Sebastian Neubauer via Phabricator via llvm-commits]

sebastian-ne marked 2 inline comments as done.
sebastian-ne added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h:494-495
 
+  /// When spilling SGPRs, we may need a temporary stack slot to free a VGPR.
+  Optional<int> SpillSGPRTmpIndex;
+
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arsenm wrote:
> sebastian-ne wrote:
> > arsenm wrote:
> > > Why doesn't this use the normal emergency stack slot?
> > How do I get the emergency stack slot?
> You don't get it, it just is what automatically happens when you attempt to use the scavenger and it fails to find a free register. It's possible we would need to add SGPR  spills as one of the conditions where it will be necessary
Thanks for the explanation. The RegScavenger won’t spill all lanes though. Also, it won’t spill if the register is dead in the currently active lanes (which we want to fix here).
So, I don’t think using the scavenger works, unless we can tell the RegScavenger to spill the whole wave, and lower that to spill – flip exec – spill – flip exec again.


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https://reviews.llvm.org/D96336