[PATCH] D97459: [CodeGen] Fix issues with subvector intrinsic index types

Fraser Cormack via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Feb 25 03:39:14 PST 2021


frasercrmck created this revision.
frasercrmck added reviewers: craig.topper, david-arm, sdesmalen, efriedma, kmclaughlin, rengolin.
Herald added subscribers: luismarques, apazos, sameer.abuasal, s.egerton, Jim, jocewei, PkmX, arphaman, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, kristof.beyls.
frasercrmck requested review of this revision.
Herald added subscribers: llvm-commits, MaskRay.
Herald added a project: LLVM.

This patch addresses issues arising from the fact that the index type
used for subvector insertion/extraction is inconsistent between the
intrinsics and SDNodes. The intrinsic forms require i64 whereas the
SDNodes use the type returned by SelectionDAG::getVectorIdxTy.

Rather than update the intrinsic definitions to use an overloaded index
type, this patch fixes the issue by transforming the index to the
correct type as required. Any loss of index bits going from i64 to a
smaller type is unexpected, and will be caught by an assertion in
SelectionDAG::getVectorIdxConstant.

The patch also updates the documentation for INSERT_SUBVECTOR and adds
an assertion to its creation to bring it in line with EXTRACT_SUBVECTOR.
This necessitated changes to AArch64 which was using i64 for
EXTRACT_SUBVECTOR but i32 for INSERT_SUBVECTOR. Only one test changed
its codegen after updating the backend accordingly.

I can undo the changes to AArch64 if that's not desired.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97459

Files:
  llvm/include/llvm/CodeGen/ISDOpcodes.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
  llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll

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