[PATCH] D97440: [LegalizeTypes] Improve ExpandIntRes_XMULO codegen.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, efriedma.
Herald added subscribers: jrtc27, fedor.sergeev, hiraditya, nemanjai, jyknight.
craig.topper requested review of this revision.
Herald added a project: LLVM.

The code previously used two BUILD_PAIRs to concatenate the two UMULO
results with 0s in the lower bits to match original VT. Then it created
an ADD and a UADDO with the original bit width. Each of those operations
need to be expanded since they have illegal types.

Since we put 0s in the lower bits before the ADD, the lower half of the
ADD result will be 0. So the lower half of the UADDO result is
solely determined by the other operand. Since the UADDO need to
be split in half, we don't really needd an operation for the lower
bits. Unfortunately, we don't see that in type legalization and end up
creating a split SETCC to legalize the UADDO. DAG combine or
lowering isn't always able to recover it.

This patch directly generates the narrower ADD and UADDO to avoid
needing to legalize them. Now only the MUL is done on the original
type.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97440

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/test/CodeGen/AArch64/umulo-128-legalisation-lowering.ll
  llvm/test/CodeGen/AArch64/vec_umulo.ll
  llvm/test/CodeGen/PowerPC/pr45448.ll
  llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
  llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll

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