[PATCH] D96980: [amdgpu] Revert agnostic SGPR spill.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D96980#2585083 <https://reviews.llvm.org/D96980#2585083>, @sebastian-ne wrote:

> Fine with me. It would be nice if someone knowledgable of LLVM can say if relying on `exec != 0` in MIR works or not.
>
> (I get the argument that IR does not run code if exec = 0, however, MIR models the hardware rather than a high-level language, and exec = 0 is perfectly fine there and even required in some cases, like for the last null export inserted in SIInsertSkips.)

I'm not convinced this always works. It's possible some transformation ends up violating this. We need to track both sets of predecessors and add some verification for this


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