[PATCH] D97319: [RISCV] Support fixed vector extract element. Use VL=1 for scalable vector extract element.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll:21
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
+; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
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frasercrmck wrote:
> I suppose this in theory could also be done with a VL set to 1. I doubt it'd be any more performant, but it'd save a `vsetvli` in this situation?
The way the vfmv.f.s pseudo is set up, there is no where to pass the VL. I think we can teach the RISCVCleanupVSETVLI pass to remove this though. I started on a patch for it yesterday. I'll try to finish it up today.


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https://reviews.llvm.org/D97319