[PATCH] D96980: [amdgpu] Revert agnostic SGPR spill.

[Sebastian Neubauer via Phabricator via llvm-commits]

sebastian-ne added a comment.

Fine with me. It would be nice if someone knowledgable of LLVM can say if relying on `exec != 0` in MIR works or not.

(I get the argument that IR does not run code if exec = 0, however, MIR models the hardware rather than a high-level language, and exec = 0 is perfectly fine there and even required in some cases, like for the last null export inserted in SIInsertSkips.)



================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:1233-1234
+
+      if (NumSubRegs > 1)
+        MIB.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
     }
----------------
Shouldn’t this still define SuperReg on the first v_readfirstlane, like before?


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  https://reviews.llvm.org/D96980/new/

https://reviews.llvm.org/D96980