[PATCH] D97276: [CodeGen] Canonicalise adds/subs of i1 vectors using XOR
David Sherwood via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 24 01:28:40 PST 2021
david-arm marked an inline comment as done.
david-arm added inline comments.
================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5312
return N1;
+ if (Opcode == ISD::ADD && VT.isVector() &&
+ VT.getVectorElementType() == MVT::i1)
----------------
craig.topper wrote:
> Isn't this also possible for sub?
Yes it is - this is what the X86 target already seems to do. Thanks for the suggestion!
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D97276/new/
https://reviews.llvm.org/D97276
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