[PATCH] D97264: [RISCV] Define types for Zvlsseg.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 23 14:48:37 PST 2021
craig.topper added inline comments.
================
Comment at: clang/include/clang/Basic/RISCVVTypes.def:59
#ifndef RVV_VECTOR_TYPE_FLOAT
#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF) \
RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true)
----------------
Do we still need NF on these macros if tuples have their own macros?
================
Comment at: clang/include/clang/Basic/RISCVVTypes.def:64
+#ifndef RVV_TUPLE
+#define RVV_TUPLE(Name, ElemId, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false)
+#endif
----------------
What is the last macro argument? This names it "false"
================
Comment at: clang/lib/Sema/Sema.cpp:392
addImplicitTypedef(Name, Context.SingletonId);
+#define RVV_TUPLE(Name, ElemId, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false) \
+ addImplicitTypedef(Name, Context.SingletonId);
----------------
This also calls the last argument "false"
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D97264/new/
https://reviews.llvm.org/D97264
More information about the llvm-commits
mailing list