[llvm] 8fa2bba - [ARM] Mir test for pre/postinc ldstopt combines. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 23 14:27:21 PST 2021
Author: David Green
Date: 2021-02-23T22:27:06Z
New Revision: 8fa2bbaed9252b217105ea332be8a0a85492099b
URL: https://github.com/llvm/llvm-project/commit/8fa2bbaed9252b217105ea332be8a0a85492099b
DIFF: https://github.com/llvm/llvm-project/commit/8fa2bbaed9252b217105ea332be8a0a85492099b.diff
LOG: [ARM] Mir test for pre/postinc ldstopt combines. NFC
Added:
llvm/test/CodeGen/ARM/store-prepostinc.mir
llvm/test/CodeGen/Thumb2/store-prepostinc.mir
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/store-prepostinc.mir b/llvm/test/CodeGen/ARM/store-prepostinc.mir
new file mode 100644
index 000000000000..d4e3fe160061
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/store-prepostinc.mir
@@ -0,0 +1,449 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -run-pass=arm-ldst-opt %s -o - | FileCheck %s
+
+--- |
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+ target triple = "thumbv7a-none-unknown-eabi"
+
+ define i8* @STR_pre4(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_pre8(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_pre255(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_pre256(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_pre1024(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_pre4095(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_pre4096(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_prem1024(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_prem4095(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_prem4096(i8* %p, i32 %v) { unreachable }
+
+ define i8* @STR_post4(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_post8(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_post255(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_post256(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_post1024(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_post4095(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_post4096(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_postm1024(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_postm4095(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_postm4096(i8* %p, i32 %v) { unreachable }
+
+...
+---
+name: STR_pre4
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_pre4
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: early-clobber $r0 = STR_PRE_IMM killed $r1, $r0, 4, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw ADDri killed renamable $r0, 4, 14 /* CC::al */, $noreg, $noreg
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_pre8
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_pre8
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: renamable $r0 = nuw ADDri killed renamable $r0, 8, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw ADDri killed renamable $r0, 8, 14 /* CC::al */, $noreg, $noreg
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_pre255
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_pre255
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: renamable $r0 = nuw ADDri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw ADDri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_pre256
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_pre256
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: renamable $r0 = nuw ADDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw ADDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_pre1024
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_pre1024
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: renamable $r0 = nuw ADDri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw ADDri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_pre4095
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_pre4095
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: renamable $r0 = nuw ADDri killed renamable $r0, 4095, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw ADDri killed renamable $r0, 4095, 14 /* CC::al */, $noreg, $noreg
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_pre4096
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_pre4096
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: renamable $r0 = nuw ADDri killed renamable $r0, 4096, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw ADDri killed renamable $r0, 4096, 14 /* CC::al */, $noreg, $noreg
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_prem1024
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_prem1024
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: renamable $r0 = nuw SUBri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw SUBri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_prem4095
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_prem4095
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: renamable $r0 = nuw SUBri killed renamable $r0, 4095, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw SUBri killed renamable $r0, 4095, 14 /* CC::al */, $noreg, $noreg
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_prem4096
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_prem4096
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: renamable $r0 = nuw SUBri killed renamable $r0, 4096, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw SUBri killed renamable $r0, 4096, 14 /* CC::al */, $noreg, $noreg
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+
+---
+name: STR_post4
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_post4
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: early-clobber $r0 = STR_POST_IMM killed $r1, $r0, $noreg, 4, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ renamable $r0 = nuw ADDri killed renamable $r0, 4, 14 /* CC::al */, $noreg, $noreg
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_post8
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_post8
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: renamable $r0 = nuw ADDri killed renamable $r0, 8, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ renamable $r0 = nuw ADDri killed renamable $r0, 8, 14 /* CC::al */, $noreg, $noreg
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_post255
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_post255
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: renamable $r0 = nuw ADDri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ renamable $r0 = nuw ADDri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_post256
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_post256
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: renamable $r0 = nuw ADDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ renamable $r0 = nuw ADDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_post1024
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_post1024
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: renamable $r0 = nuw ADDri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ renamable $r0 = nuw ADDri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_post4095
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_post4095
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: renamable $r0 = nuw ADDri killed renamable $r0, 2095, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ renamable $r0 = nuw ADDri killed renamable $r0, 2095, 14 /* CC::al */, $noreg, $noreg
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_post4096
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_post4096
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: renamable $r0 = nuw ADDri killed renamable $r0, 4096, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ renamable $r0 = nuw ADDri killed renamable $r0, 4096, 14 /* CC::al */, $noreg, $noreg
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_postm1024
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_postm1024
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: renamable $r0 = nuw SUBri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ renamable $r0 = nuw SUBri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_postm4095
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_postm4095
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: renamable $r0 = nuw SUBri killed renamable $r0, 2095, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ renamable $r0 = nuw SUBri killed renamable $r0, 2095, 14 /* CC::al */, $noreg, $noreg
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_postm4096
+alignment: 4
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_postm4096
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: renamable $r0 = nuw SUBri killed renamable $r0, 4096, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
+ STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ renamable $r0 = nuw SUBri killed renamable $r0, 4096, 14 /* CC::al */, $noreg, $noreg
+ BX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
diff --git a/llvm/test/CodeGen/Thumb2/store-prepostinc.mir b/llvm/test/CodeGen/Thumb2/store-prepostinc.mir
new file mode 100644
index 000000000000..63493d6cc275
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/store-prepostinc.mir
@@ -0,0 +1,735 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -run-pass=arm-ldst-opt %s -o - | FileCheck %s
+
+--- |
+ target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+ target triple = "thumbv7m-none-unknown-eabi"
+
+ define i8* @STR_pre4(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_pre8(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_pre255(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_pre256(i8* %p, i32 %v) { unreachable }
+
+ define i8* @STRD_pre4(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_pre8(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_pre255(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_pre256(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_pre1020(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_pre1024(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_prem4(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_prem8(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_prem255(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_prem256(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_prem1020(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_prem1024(i8* %p, i32 %v) { unreachable }
+
+ define i8* @STR_post4(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_post8(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_post255(i8* %p, i32 %v) { unreachable }
+ define i8* @STR_post256(i8* %p, i32 %v) { unreachable }
+
+ define i8* @STRD_post4(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_post8(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_post255(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_post256(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_post1020(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_post1024(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_postm4(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_postm8(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_postm255(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_postm256(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_postm1020(i8* %p, i32 %v) { unreachable }
+ define i8* @STRD_postm1024(i8* %p, i32 %v) { unreachable }
+
+...
+---
+name: STR_pre4
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_pre4
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: early-clobber $r0 = t2STR_PRE killed $r1, $r0, 4, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 4, 14 /* CC::al */, $noreg, $noreg
+ t2STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_pre8
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_pre8
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 8, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: t2STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 8, 14 /* CC::al */, $noreg, $noreg
+ t2STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_pre255
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_pre255
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: t2STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg
+ t2STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_pre256
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_pre256
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: t2STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
+ t2STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_pre4
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_pre4
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 4, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 4, 14 /* CC::al */, $noreg, $noreg
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_pre8
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_pre8
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: $r0 = t2STRD_PRE killed renamable $r1, killed renamable $r2, killed $r0, 8, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 8, 14 /* CC::al */, $noreg, $noreg
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_pre255
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_pre255
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_pre256
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_pre256
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_pre1020
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_pre1020
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 1020, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 1020, 14 /* CC::al */, $noreg, $noreg
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_pre1024
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_pre1024
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_prem4
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_prem4
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: renamable $r0 = nuw t2SUBri killed renamable $r0, 4, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw t2SUBri killed renamable $r0, 4, 14 /* CC::al */, $noreg, $noreg
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_prem8
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_prem8
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: $r0 = t2STRD_PRE killed renamable $r1, killed renamable $r2, killed $r0, -8, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw t2SUBri killed renamable $r0, 8, 14 /* CC::al */, $noreg, $noreg
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_prem255
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_prem255
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: renamable $r0 = nuw t2SUBri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw t2SUBri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_prem256
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_prem256
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: renamable $r0 = nuw t2SUBri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw t2SUBri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_prem1020
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_prem1020
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: renamable $r0 = nuw t2SUBri killed renamable $r0, 1020, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw t2SUBri killed renamable $r0, 1020, 14 /* CC::al */, $noreg, $noreg
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_prem1024
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_prem1024
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: renamable $r0 = nuw t2SUBri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ renamable $r0 = nuw t2SUBri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+
+---
+name: STR_post4
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_post4
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: early-clobber $r0 = t2STR_POST killed $r1, $r0, 4, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ t2STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 4, 14 /* CC::al */, $noreg, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_post8
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_post8
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: t2STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 8, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ t2STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 8, 14 /* CC::al */, $noreg, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_post255
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_post255
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: t2STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ t2STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STR_post256
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1
+
+ ; CHECK-LABEL: name: STR_post256
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: t2STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ t2STRi12 killed renamable $r1, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 4)
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_post4
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_post4
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 4, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 4, 14 /* CC::al */, $noreg, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_post8
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_post8
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: $r0 = t2STRD_POST killed renamable $r1, killed renamable $r2, killed $r0, 8, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 8, 14 /* CC::al */, $noreg, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_post255
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_post255
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_post256
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_post256
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_post1020
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_post1020
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 1020, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 1020, 14 /* CC::al */, $noreg, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_post1024
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_post1024
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_postm4
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_postm4
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: renamable $r0 = nuw t2SUBri killed renamable $r0, 4, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ renamable $r0 = nuw t2SUBri killed renamable $r0, 4, 14 /* CC::al */, $noreg, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_postm8
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_postm8
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: $r0 = t2STRD_POST killed renamable $r1, killed renamable $r2, killed $r0, -8, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ renamable $r0 = nuw t2SUBri killed renamable $r0, 8, 14 /* CC::al */, $noreg, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_postm255
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_postm255
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: renamable $r0 = nuw t2SUBri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ renamable $r0 = nuw t2SUBri killed renamable $r0, 255, 14 /* CC::al */, $noreg, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_postm256
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_postm256
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: renamable $r0 = nuw t2ADDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ renamable $r0 = nuw t2ADDri killed renamable $r0, 256, 14 /* CC::al */, $noreg, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_postm1020
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_postm1020
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: renamable $r0 = nuw t2SUBri killed renamable $r0, 1020, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ renamable $r0 = nuw t2SUBri killed renamable $r0, 1020, 14 /* CC::al */, $noreg, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
+---
+name: STRD_postm1024
+alignment: 2
+tracksRegLiveness: true
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+body: |
+ bb.0 (%ir-block.0):
+ liveins: $r0, $r1, $r2
+
+ ; CHECK-LABEL: name: STRD_postm1024
+ ; CHECK: liveins: $r0, $r1, $r2
+ ; CHECK: t2STRDi8 killed $r1, killed $r2, $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ ; CHECK: renamable $r0 = nuw t2SUBri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg
+ ; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+ t2STRDi8 killed renamable $r1, killed renamable $r2, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store 8)
+ renamable $r0 = nuw t2SUBri killed renamable $r0, 1024, 14 /* CC::al */, $noreg, $noreg
+ tBX_RET 14 /* CC::al */, $noreg, implicit $r0
+
+...
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