[PATCH] D97319: [RISCV] Support fixed vector extract element. Use VL=1 for scalable vector extract element.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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I've changed to use VL=1 for slidedown and shifts to avoid extra
element processing that we don't need.

The i64 fixed vector handling on i32 isn't great if the vector type
isn't legal due to an ordering issue in type legalization. If the
vector type isn't legal, we fall back to default legalization
which will bitcast the vector to vXi32 and use two independent extracts.
Doing better will require handling several different cases by
manually inserting insert_subvector/extract_subvector to adjust the type
to a legal vector before emitting custom nodes.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97319

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll

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