[PATCH] D96336: [AMDGPU] Save VGPR of whole wave when spilling

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D96336#2553296 <https://reviews.llvm.org/D96336#2553296>, @kerbowa wrote:

> In D96336#2553008 <https://reviews.llvm.org/D96336#2553008>, @critson wrote:
>
>> If every SGPR spill that goes to scratch has to do an extra store+load (or multiple) then is that not potentially worse than the performance hit of reserving an entire VGPR for spilling in the case that we know we are going to have to use one? (I guess perhaps we have no way of knowing we need one?)
>
> We currently unconditionally reserve one VGPR for SGPR spills. I'm working on changing this so that we have the option of reserving a variable amount of VGPRs based on some register pressure threshold. Spilling SGPRs to memory should be a last resort anyway, and I've seen the issue raised in this patch multiple times. It's worth having something less broken when we run out of lanes in reserved VGPRs.

We don't need a pressure heuristic to decide to reserve VGPRs ahead of time, we can just split the allocation process as in D55301 <https://reviews.llvm.org/D55301>


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