[PATCH] D97280: [AArch64] Extend vecreduce -> udot handling to mla reductions

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: mivnay, SjoerdMeijer, fhahn, efriedma, NickGuy.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
dmgreen requested review of this revision.
Herald added a project: LLVM.

We previously had lowering for:

  vecreduce.add(zext(X)) to vecreduce.add(UDOT(zero, X, one))

This extends that to also handle:

  vecreduce.add(mul(zext(X), zext(Y)) to vecreduce.add(UDOT(zero, X, Y))

It extends the existing code to optionally handle a mul with equal extends.


https://reviews.llvm.org/D97280

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/neon-dotreduce.ll

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