[PATCH] D95432: AMDGPU/GlobalISel: Combine uniform icmp

Tue Feb 23 06:02:41 PST 2021

arsenm added a comment.

In D95432#2581586 <https://reviews.llvm.org/D95432#2581586>, @foad wrote:

> In D95432#2573444 <https://reviews.llvm.org/D95432#2573444>, @arsenm wrote:
>
>> In D95432#2573420 <https://reviews.llvm.org/D95432#2573420>, @arsenm wrote:
>>
>>> Actually, why is this patch necessary? The ZEXT+TRUNC handling takes care of this already?
>>
>> Oh right, the problem here is actually the intermediate SCC copies produced as a selection artifact.
>>
>> I'm not sure treating this as a combine is the correct way to go about this. The DAG handles this with a scheduler to minimize physical register liveranges. We might be better treating this off as a scheduling issue for after selection, when we directly see the SCC defs.
>
> For the case I looked at (test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll) just running zext_trunc_fold as a post-regbankselect combine was enough to get rid of the SCC copies. So perhaps we should commit that first, and then worry about how to handle the remaining cases?

Yes, these are unrelated problems

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https://reviews.llvm.org/D95432