[llvm] 53c4c2b - [RISCV] vle1.v/vse1.v should be unmasked instructions.

[Hsiangkai Wang via llvm-commits]

Author: Hsiangkai Wang
Date: 2021-02-23T19:59:22+08:00
New Revision: 53c4c2b9f7328a8b80ecfd1fc60387d0f910cc2f

URL: https://github.com/llvm/llvm-project/commit/53c4c2b9f7328a8b80ecfd1fc60387d0f910cc2f
DIFF: https://github.com/llvm/llvm-project/commit/53c4c2b9f7328a8b80ecfd1fc60387d0f910cc2f.diff

LOG: [RISCV] vle1.v/vse1.v should be unmasked instructions.

vle1.v/vse1.v should be unmasked instructions. The vm encoding is 1 for
unmasked instructions.

Differential Revision: https://reviews.llvm.org/D97237

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    llvm/test/MC/RISCV/rvv/load.s
    llvm/test/MC/RISCV/rvv/store.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 9b2c0a20f5fd..3351b9aa01fd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -86,7 +86,9 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
 class VUnitStrideLoadMask<string opcodestr>
     : RVInstVLU<0b000, LSWidth8.Value{3}, LUMOPUnitStrideMask, LSWidth8.Value{2-0},
                 (outs VR:$vd),
-                (ins GPR:$rs1), opcodestr, "$vd, (${rs1})">;
+                (ins GPR:$rs1), opcodestr, "$vd, (${rs1})"> {
+  let vm = 1;
+}
 
 // load vd, (rs1), vm
 class VUnitStrideLoad<RISCVLSUMOP lumop, RISCVWidth width,
@@ -143,11 +145,13 @@ class VIndexedSegmentLoad<bits<3> nf, RISCVMOP mop, RISCVWidth width,
 } // hasSideEffects = 0, mayLoad = 1, mayStore = 0
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
-// store vd, vs3, (rs1), vm
+// store vd, vs3, (rs1)
 class VUnitStrideStoreMask<string opcodestr>
     : RVInstVSU<0b000, LSWidth8.Value{3}, SUMOPUnitStrideMask, LSWidth8.Value{2-0},
                 (outs), (ins VR:$vs3, GPR:$rs1), opcodestr,
-                "$vs3, (${rs1})">;
+                "$vs3, (${rs1})"> {
+  let vm = 1;
+}
 
 // store vd, vs3, (rs1), vm
 class VUnitStrideStore<RISCVLSUMOP sumop, RISCVWidth width,

diff  --git a/llvm/test/MC/RISCV/rvv/load.s b/llvm/test/MC/RISCV/rvv/load.s
index 3d0dbb15c36e..e0120be25115 100644
--- a/llvm/test/MC/RISCV/rvv/load.s
+++ b/llvm/test/MC/RISCV/rvv/load.s
@@ -10,9 +10,9 @@
 
 vle1.v v8, (a0)
 # CHECK-INST: vle1.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x00]
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 b5 00 <unknown>
+# CHECK-UNKNOWN: 07 04 b5 02 <unknown>
 
 vle8.v v8, (a0), v0.t
 # CHECK-INST: vle8.v v8, (a0), v0.t

diff  --git a/llvm/test/MC/RISCV/rvv/store.s b/llvm/test/MC/RISCV/rvv/store.s
index e4795aa1c2c9..7200f04d8a2b 100644
--- a/llvm/test/MC/RISCV/rvv/store.s
+++ b/llvm/test/MC/RISCV/rvv/store.s
@@ -10,9 +10,9 @@
 
 vse1.v v24, (a0)
 # CHECK-INST: vse1.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x00]
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 0c b5 00 <unknown>
+# CHECK-UNKNOWN: 27 0c b5 02 <unknown>
 
 vse8.v v24, (a0), v0.t
 # CHECK-INST: vse8.v v24, (a0), v0.t