[PATCH] D97237: [RISCV] vle1.v/vse1.v should be unmasked instructions.

[Hsiangkai Wang via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG53c4c2b9f732: [RISCV] vle1.v/vse1.v should be unmasked instructions. (authored by HsiangKai).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97237/new/

https://reviews.llvm.org/D97237

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/MC/RISCV/rvv/load.s
  llvm/test/MC/RISCV/rvv/store.s


Index: llvm/test/MC/RISCV/rvv/store.s
===================================================================
--- llvm/test/MC/RISCV/rvv/store.s
+++ llvm/test/MC/RISCV/rvv/store.s
@@ -10,9 +10,9 @@
 
 vse1.v v24, (a0)
 # CHECK-INST: vse1.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x0c,0xb5,0x00]
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 0c b5 00 <unknown>
+# CHECK-UNKNOWN: 27 0c b5 02 <unknown>
 
 vse8.v v24, (a0), v0.t
 # CHECK-INST: vse8.v v24, (a0), v0.t
Index: llvm/test/MC/RISCV/rvv/load.s
===================================================================
--- llvm/test/MC/RISCV/rvv/load.s
+++ llvm/test/MC/RISCV/rvv/load.s
@@ -10,9 +10,9 @@
 
 vle1.v v8, (a0)
 # CHECK-INST: vle1.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x00]
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 b5 00 <unknown>
+# CHECK-UNKNOWN: 07 04 b5 02 <unknown>
 
 vle8.v v8, (a0), v0.t
 # CHECK-INST: vle8.v v8, (a0), v0.t
Index: llvm/lib/Target/RISCV/RISCVInstrInfoV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -86,7 +86,9 @@
 class VUnitStrideLoadMask<string opcodestr>
     : RVInstVLU<0b000, LSWidth8.Value{3}, LUMOPUnitStrideMask, LSWidth8.Value{2-0},
                 (outs VR:$vd),
-                (ins GPR:$rs1), opcodestr, "$vd, (${rs1})">;
+                (ins GPR:$rs1), opcodestr, "$vd, (${rs1})"> {
+  let vm = 1;
+}
 
 // load vd, (rs1), vm
 class VUnitStrideLoad<RISCVLSUMOP lumop, RISCVWidth width,
@@ -143,11 +145,13 @@
 } // hasSideEffects = 0, mayLoad = 1, mayStore = 0
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
-// store vd, vs3, (rs1), vm
+// store vd, vs3, (rs1)
 class VUnitStrideStoreMask<string opcodestr>
     : RVInstVSU<0b000, LSWidth8.Value{3}, SUMOPUnitStrideMask, LSWidth8.Value{2-0},
                 (outs), (ins VR:$vs3, GPR:$rs1), opcodestr,
-                "$vs3, (${rs1})">;
+                "$vs3, (${rs1})"> {
+  let vm = 1;
+}
 
 // store vd, vs3, (rs1), vm
 class VUnitStrideStore<RISCVLSUMOP sumop, RISCVWidth width,


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