[PATCH] D97130: [RISCV] Have sexti32 also recognize AssertZExt from types smaller than i32.

Mon Feb 22 14:51:26 PST 2021

craig.topper added inline comments.

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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoF.td:403
 // [u]int->fp. Match GCC and default to using dynamic rounding mode.
-def : Pat<(sint_to_fp (i64 (sexti32 GPR:$rs1))), (FCVT_S_W $rs1, 0b111)>;
+def : Pat<(sint_to_fp (i64 (sexti32 i64:$rs1))), (FCVT_S_W $rs1, 0b111)>;
 def : Pat<(uint_to_fp (i64 (zexti32 GPR:$rs1))), (FCVT_S_WU $rs1, 0b111)>;
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jrtc27 wrote:
> luismarques wrote:
> > craig.topper wrote:
> > > The i64 instead of GPR here tricks tablegen into not generating extra patterns for RV32.
> > I think there would be a benefit in adding this as a code comment. In at least one of the tablegen files, if not all of them.
> Does `(i64 GPR:$rs1)` also achieve the same effect like is used on lines 405 and 406? That'd be nicer if it works IMO. Also I think it'd be worthwhile having `zexti32` be consistent with `sexti32` even if not strictly necessary; currently the difference is rather odd.
That does work so I'll switch to that. I'll move zexti32 in a followup  patch. It's a little weirder since we have to look at the mask on an AND and use computeKnownBits to match the behavior of OPC_CheckAndImm. I think we might be able to call into the code in SelectionDAGISel.cpp that handles that.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97130/new/

https://reviews.llvm.org/D97130