[PATCH] D96972: [RISCV] Support insertion of misaligned subvectors
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 22 11:58:05 PST 2021
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.
LGTM other than that one question
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2265
+ SDLoc DL(Op);
+ auto OrigIdx = Op.getConstantOperandVal(2);
+ const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo();
----------------
Should this be unsigned instead of auto? I think getConstantOperandVal returns uint64_t but the rest of this code uses unsigned. I probably should have asked this question in the EXTRACT_SUBVECTOR patch.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D96972/new/
https://reviews.llvm.org/D96972
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