[PATCH] D94708: [IR] Introduce llvm.experimental.vector.splice intrinsic

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp:940
+  case ISD::VECTOR_SPLICE:
+    SplitVecRes_LOAD(cast<LoadSDNode>(TLI.expandVectorSplice(N, DAG)), Lo, Hi);
+    break;
----------------
paulwalker-arm wrote:
> This doesn't look great to me because it ties the hands of expandVectorSplice, whose name does not suggest it must return a load.  If you prefer not to explicitly create the split loads then it seems more natural, and future proof, if the result of expandVectorSplice is split using a pair of EXTRACT_SUBVECTOR operations.
> This doesn't look great to me because it ties the hands of expandVectorSplice, whose name does not suggest it must return a load.  If you prefer not to explicitly create the split loads then it seems more natural, and future proof, if the result of expandVectorSplice is split using a pair of EXTRACT_SUBVECTOR operations.

Fair point, I've used EXTRACT_SUBVECTOR instead. I should point out warnings were being generated for the `nxv16f32` splitvec tests by the `getVectorNumElements` call in `DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR`. To remove the warnings I changed it to `getVectorMinNumElements`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94708/new/

https://reviews.llvm.org/D94708