[llvm] 6ff09ce - [AArch64][GlobalISel] Fix <16 x s8> G_DUP regbankselect to assign source to gpr.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2021-02-21T21:17:29-08:00
New Revision: 6ff09ce061df499b518150f33006d1b0dcfdabd7

URL: https://github.com/llvm/llvm-project/commit/6ff09ce061df499b518150f33006d1b0dcfdabd7
DIFF: https://github.com/llvm/llvm-project/commit/6ff09ce061df499b518150f33006d1b0dcfdabd7.diff

LOG: [AArch64][GlobalISel] Fix <16 x s8> G_DUP regbankselect to assign source to gpr.

We can only select this type if the source is on GPR, not FPR.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index 0e12fff100c2..cbc027c3c095 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -666,9 +666,12 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   switch (Opc) {
   case AArch64::G_DUP: {
     Register ScalarReg = MI.getOperand(1).getReg();
+    LLT ScalarTy = MRI.getType(ScalarReg);
     auto ScalarDef = MRI.getVRegDef(ScalarReg);
-    if (getRegBank(ScalarReg, MRI, TRI) == &AArch64::FPRRegBank ||
-        onlyDefinesFP(*ScalarDef, MRI, TRI))
+    // s8 is an exception for G_DUP, which we always want on gpr.
+    if (ScalarTy.getSizeInBits() != 8 &&
+        (getRegBank(ScalarReg, MRI, TRI) == &AArch64::FPRRegBank ||
+         onlyDefinesFP(*ScalarDef, MRI, TRI)))
       OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
     else
       OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR};

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir
index 72407051cd33..4cd6eef531ce 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir
@@ -152,3 +152,26 @@ body:             |
     RET_ReallyLR implicit $q0
 
 ...
+---
+name:            v416s8_gpr
+alignment:       4
+legalized:       true
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $w0
+
+    ; CHECK-LABEL: name: v416s8_gpr
+    ; CHECK: liveins: $w0
+    ; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
+    ; CHECK: %trunc:gpr(s8) = G_TRUNC [[COPY]](s32)
+    ; CHECK: [[DUP:%[0-9]+]]:fpr(<16 x s8>) = G_DUP %trunc(s8)
+    ; CHECK: $q0 = COPY [[DUP]](<16 x s8>)
+    ; CHECK: RET_ReallyLR implicit $q0
+    %0:_(s32) = COPY $w0
+    %trunc:_(s8) = G_TRUNC %0(s32)
+    %1:_(<16 x s8>) = G_DUP %trunc(s8)
+    $q0 = COPY %1(<16 x s8>)
+    RET_ReallyLR implicit $q0
+
+...