[PATCH] D97172: [AVR] Fix lifeness issues in the AVR backend

[Ayke via Phabricator via llvm-commits]

aykevl created this revision.
aykevl added reviewers: dylanmckay, benshi001.
Herald added subscribers: Jim, hiraditya.
aykevl requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

This patch is a large number of small changes that should hopefully not
affect the generated machine code but are still important to get right
so that the machine verifier won't complain about them. It is the last
in a series of patches to get all the AVR codegen tests to pass with the
machine verifier enabled.

The llvm/test/CodeGen/AVR/pseudo/*.mir changes are also necessary
because without the liveins the used registers are considered undefined
by the machine verifier and it will complain about them.

---

I'm aware there are other issues that trigger the machine verifier in the AVR backend, but this series of patches should at least get `ninja -j4 check-llvm-codegen-avr` to work with the machine verifier enabled. Actually enabling it for the AVR backend will need to be done in a separate patch (`isMachineVerifierClean`).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D97172

Files:
  llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
  llvm/lib/Target/AVR/AVRFrameLowering.cpp
  llvm/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
  llvm/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
  llvm/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
  llvm/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
  llvm/test/CodeGen/AVR/pseudo/ASRWRd.mir
  llvm/test/CodeGen/AVR/pseudo/COMWRd.mir
  llvm/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
  llvm/test/CodeGen/AVR/pseudo/CPWRdRr.mir
  llvm/test/CodeGen/AVR/pseudo/EORWRdRr.mir
  llvm/test/CodeGen/AVR/pseudo/FRMIDX.mir
  llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
  llvm/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
  llvm/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
  llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
  llvm/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
  llvm/test/CodeGen/AVR/pseudo/LSLWRd.mir
  llvm/test/CodeGen/AVR/pseudo/LSRWRd.mir
  llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir
  llvm/test/CodeGen/AVR/pseudo/ORIWRdK.mir
  llvm/test/CodeGen/AVR/pseudo/ORWRdRr.mir
  llvm/test/CodeGen/AVR/pseudo/OUTWARr.mir
  llvm/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
  llvm/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
  llvm/test/CodeGen/AVR/pseudo/SEXT.mir
  llvm/test/CodeGen/AVR/pseudo/STSWKRr.mir
  llvm/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
  llvm/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
  llvm/test/CodeGen/AVR/pseudo/STWPtrRr.mir
  llvm/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
  llvm/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
  llvm/test/CodeGen/AVR/pseudo/ZEXT.mir

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