[PATCH] D97133: [SelectionDAG][RISCV] Teach ComputeNumSignBits to handle SREM.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Feb 21 11:17:29 PST 2021


This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1a6c1ac6862a: [SelectionDAG][RISCV] Teach ComputeNumSignBits to handle SREM. (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97133/new/

https://reviews.llvm.org/D97133

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoM.td
  llvm/test/CodeGen/Mips/llvm-ir/srem.ll
  llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll

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