[PATCH] D97133: [SelectionDAG][RISCV] Teach ComputeNumSignBits to handle SREM.

[Luís Marques via Phabricator via llvm-commits]

luismarques added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:3877
+    // at least as many sign bits as the left hand side.
+    return ComputeNumSignBits(Op.getOperand(0), DemandedElts, Depth + 1);
   case ISD::TRUNCATE: {
----------------
RKSimon wrote:
> This is a lot more relaxed than ValueTracking ?
Interesting! ValueTracking seems to abort on `!Denominator->isStrictlyPositive()`. When I reviewed the logic of this code at first I thought there would be cases where it would break, but when I thought about it more deeply it all seemed fine. Now I'm curious about what may explain the divergence. Maybe the implementation in ValueTracking was considering modulus instead of remainder?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D97133/new/

https://reviews.llvm.org/D97133